1. Technical Field of the Invention
The invention relates generally to electronic devices; and, more particularly, it relates to interfacing of FPGAs (Filed Programmable Logic Arrays) within various electronic devices.
2. Description of Related Art
As is known in the art of designing and building various electronic devices, one of the difficult tasks presented is the efficient allocation of resources for use by any one or more functional blocks within a device. When even considering the various basic functionality of a microprocessor within a device, there seems always to be the various design challenges to ensure sufficient (yet efficient) amount of memory (including both on-chip and off-chip in some instances), sufficient peripheral support, sufficient amount of IOs (Input/Output devices and/or ports), and so on. Once a designer decides on a particular implementation and the amounts of such processing and support allocation (e.g., amounts of memory, peripheral support, IOs, and so on), there is typically great inflexibility in changing those allocations for a particular device. Certainly, knowledge (either good or bad) may be acquired for a particular device, and that knowledge may be used to allow for a more efficient allocation of resources in a next-generation device. However, this does not help the present device to perform any more efficiently in terms of the allocation and usage of resources.
Within more complex devices that include a wider variety of functional blocks, some of these functional blocks may actually include an appropriate amount of support resources. However, as is oftentimes the case, a functional block includes too little support resources (e.g., memory, processing functionality, IOs, etc.) or there are many support resources that go unused. For example, one functional block in a device may be using all (e.g., to capacity) of the support resources provided there to. Another functional block in the same device may have a large amount of support resources available that are simply sitting idly and performing no functions whatsoever; or else, these support resources may be used on a relatively infrequent basis.
The static and one-time design of such prior art devices shows their inflexibility to accommodate changing needs or operating conditions in terms of their support resources. That is to say, once a design is made, the user simply needs to deal with the existent and dedicated support resources for the various functional blocks included within a device. While some support resources can be upgraded (e.g., memory), the vast majority of such support resources cannot be modified once the device is made (e.g., number of IOs of an integrated circuit). A common approach is simply to over-allocate support resources for various functional blocks to ensure that the capabilities of these support resources will not (ideally, never) be saturated. However, this often results in a high degree of waste, in that, such support resources are simply sitting idly and being unused. As such, it is clear there is a need in the art for some means by which greater flexibility may be provided to the various functional blocks within devices to accommodate changing needs and/or operating conditions of the device
FIG. 1 is a diagram illustrating a prior art embodiment of FPGAs (Field Programmable Gate Arrays) operating such that each FPGA has its own dedicated resources. A number of FPGAs (shown as FPGA 110, FPGA 120, and FPGA 130) are all interconnected via an FPGA interconnection 101. It is noted that the FPGA interconnection 101 is typically implemented using a number of parallel buses that interconnect each of the individual functional components of each of the FPGAs. This can be a very inefficient and cumbersome way in which to interface the various FPGAs.
Each of the FPGAs includes various types of functionality. For example, the FPGA 110 includes embedded processing functionality 112, block memory 114, and CLBs (Configurable Logic Blocks) 116. The embedded processing functionality 112 may be an actual integrated circuit that is operable to perform various digital signal processing functions, such as multiplication. The block memory 114, such as a block random access memory (BRAM), may be used by the embedded processing functionality 112. The CLBs 116 may be viewed as being reconfigurable circuitry that is able to support various logic functions such as OR gates, AND gates, NAND gates, XOR gates, among other types of logic functions. Generally speaking, the CLBs 116 may be viewed as being reconfigurable circuitry that is operable to be implemented to support and perform any of a wide variety of logic functional processing including various logic functions having various numbers of inputs and outputs. Each of the other FPGA 120 and FPGA 130 includes its corresponding dedicated support resources as well. For example, the FPGA 120 includes embedded processing functionality 122, block memory 124, and CLBs 126, and the FPGA 130 includes embedded processing functionality 132, block memory 134, and CLBs 136. A description of a conventional FPGA is found in the Virtex-II Pro Platform FPGA Handbook, October 2002, from Xilinx Inc. of San Jose, Calif.
Again, an mentioned above, each of the individual functional components of each of the FPGAs is interconnected via the FPGA interconnection 101 using various parallel buses included therein. For example, when the embedded processing functionality 112 is to be communicatively coupled to either the embedded processing functionality 122 or the embedded processing functionality 132, or vice versa, then a relatively large parallel bus is employed to perform this actual interfacing. Similarly, when the block memory 114 is to be communicatively coupled to either the block memory 124 or the block memory 134, or vice versa, then a relatively large parallel bus is employed to perform this actual interfacing. Lastly, as shown within this example embodiment, when the CLBs 116 are to be communicatively coupled to either the CLBs 126 or the CLBs 136, then a relatively large parallel bus is also employed to perform this actual interfacing. The number of parallel lines within each of the various types of parallel buses that are employed to communicatively couple each of the various types of individual functional components within each of the FPGAs may vary in size and number. Clearly, this is a prior art approach to interfacing the various individual functional components within each of the FPGAs can be very intensive and cumbersome.
The manner in which communication is performed along these various parallel buses can be unique for various types of FPGA applications. That is to say, different users may implement the interfacing in different manners. This variability in the manner by which the individual functional components within each of the FPGAs are interfaced only contributes to the lack of uniformity and commonality of the manner by which the various FPGAs operate within a larger application.
This multiple FPGA arrangement can suffer from many of the deficiencies described above, in that, each of the individual FPGAs sometimes does not have a sufficient amount of support resources available to perform the functionality it is intended to do. Block memory is one particular type of support resource that is typically consumed and capitalized upon very quickly. When the block memory of any FPGA is consumed, then a quick solution approach is simply to use the available CLBs on that particular FPGA. However, this is a very inefficient usage of the CLB functionality provided by an FPGA. The inflexibility of this prior art approach, in that, each FPGA is limited to the support resources that have been implemented therein can present difficulty in various designs. Moreover, even when designers seek to try to interface one FPGA to another, there does not exist in the art a common means or approach by which this can be done. There is an extremely large number of means by which this interfacing may be performed, and it can vary greatly from one implementation to another. Clearly, there is a need in the art to allow for a better means of interfacing FPGAs to one another and also a means that can address the design challenges and inflexibility of statically dedicated support resources within an FPGA.